Conventionally, trench gate-type semiconductor devices having a trench gate structure have been hitherto proposed as an insulated gate-type semiconductor device for power device applications. With this type of trench gate-type semiconductor device, high withstand voltage and low on-resistance are generally in trade-off relation.
For a trench gate-type semiconductor device designed to focus attention on the above problem, the present applicant proposed an insulated gate-type semiconductor device as shown in FIG. 24 (see JP-A-2005-142243). This insulated gate-type semiconductor device 900 is provided with an N+ source region 31, an N+ drain region 11, a P− body region 41 and an N− drift region 12. A semiconductor substrate is engraved partly at an upper surface side thereof to form a gate trench 21 passing through the P− body region 41. A deposited insulating layer 23 obtained by deposition of an insulator is formed on the bottom of the gate trench 21. Moreover, a gate electrode 22 is formed on the deposited insulating layer 23. The gate electrode 22 faces to the N+ source region 31 and P− body region 41 through a gate insulating film 24 formed on the wall surfaces of the gate trench 21. A P diffusion region 51 in a floating state is formed inside the drift region 12. The lower end of the gate trench 21 is positioned within the P diffusion region 51.
The insulated gate-type semiconductor device 900 has the following characteristics owing to the provision of the P diffusion region 51 in a floating state within the N− drift region 12 (which structure is hereinafter referred to as a “floating structure”).
With this insulated gate-type semiconductor device 900, when the gate voltage is off, a depletion layer spreads from a PN junction between the N− drift region 12 and the P− body region 41. On arrival of the depletion layer at the P diffusion region 51, the P diffusion region 51 is turned into a punch-though condition, thereby fixing a potential. Moreover, because the depletion layer also spreads from a PN junction with the P diffusion region 51, a peak of field intensity is formed at the PN junction with the P diffusion region 51, aside from the PN junction with the P− body region 41. More particularly, as shown in FIG. 25, two peaks of field intensity are formed, thereby enabling a maximum peak to be reduced. Thus, high withstand voltage is realized. Because of the high withstand voltage, it becomes possible to achieve a low on-resistance by increasing an impurity concentration of the N− drift region 12. It will be noted that the mechanism of the floating structure is disclosed in detail, for example, in JP-A-9 (1997)-191109.
With an insulated gate-type semiconductor device for inverter circuit, it is usual that when a gate voltage (Vg) is turned on or off, a drain voltage (Vd) changes as indicated by the solid line of FIG. 26. More particularly, when Vg is turned on (A in FIG. 26), a depletion layer does not spread, thus permitting operation to be in a low on-resistance state. During the course where Vg is off (B in FIG. 26), the depletion layer is in a spread state (in a state of high on-resistance), under which Vd becomes high. More particularly, the withstand voltage between the drain and source is ensured by means of the depletion layer. When Vg is turned on again (C in FIG. 26), the depletion layer becomes narrowed again. This results in operation in a low on-resistance state.
However, the insulated gate-type semiconductor device having such a floating structure as set out hereinabove is more unlikely to return to the low on-resistance state when stayed at C in FIG. 26 in comparison with an ordinary insulated gate-type semiconductor device. That is, with an insulated gate-type semiconductor device having no floating structure (an ordinary insulated gate-type semiconductor device), holes are supplied from the source, so that the depletion layer is instantaneously narrowed. On the other hand, with the insulated gate-type semiconductor device having such a floating structure as shown in FIG. 24, the P diffusion region beneath the trench is in a floating state where holes are not sufficiently supplied. Accordingly, it takes a long time before the depletion layer that has spread to below the P diffusion region beneath the trench is narrowed. As a consequence, as indicated by the dotted line in FIG. 26, instantaneous return to the low on-resistance state is not realized. Thus, an adverse influence on the on-resistance characteristic is given.
Especially, with a large chip size, holes to be supplied become great in quantity. In other words, as the chip size increases, a delay is caused in supply of holes. Thus, there is concern that a switching performance degrades.
The invention has been accomplished to solve the problems involved in the afore-stated prior art insulated gate-type semiconductor devices. More particularly, an object of the invention is to provide an insulated gate-type semiconductor device, and a manufacturing method thereof, which is high in withstand voltage and wherein a good on-resistance characteristic is obtained at the time of switching operation.